Fully Depleted SOI Multiple Threshold Voltage Application

ABSTRACT

An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.

This application is a continuation of and claims the benefit of patentapplication Ser. No. 11/093,593, entitled “Fully Depleted SOI MultipleThreshold Voltage Application,” filed on Mar. 29, 2005, which claims thebenefit of U.S. Provisional Application No. 60/566,040, filed on Apr.28, 2004, entitled “Fully Depleted SOI Multiple Threshold VoltageApplication,” applications are hereby incorporated herein by reference.

TECHNICAL FIELD

The present invention relates generally to semiconductor devices, andmore particularly to a system and method for a fully depleted SOImultiple threshold voltage application.

BACKGROUND

In order to produce competitive electronic devices, it is often desiredto produce semiconductor chips with several different regions (e.g.,core region, low power region, I/O region) having semiconductor devicesthat vary according to speed and power, for example. Semiconductordevices that provide some or all of these features includesilicon-on-insulator (SOI) devices. An existing challenge in SOItechnology, however, is forming thin Si channel SOI I/O devices withsignificant voltage threshold (V_(th)) control. For example, in an SOII/O application, a higher V_(th) is necessary because SOI devices sufferfrom a larger drain induced barrier lowering (DIBL) effect (which iscaused by the floating body characteristics) than do bulk silicon waferdevices. Further, the higher voltages typically applied in the I/Oregions increase the concern regarding leakage current. Overcoming theseshortcomings will become increasingly significant as SOI devicethickness is scaled down to improve performance and to reduce thefloating body effects.

Several known methods attempt to control V_(th) by controlling the bodypotential of the SOI transistor. A first method is to tie the transistorbody to a fixed voltage level through a substrate contact. However,despite reducing the floating body effect (FBE) in SOI devices, thebody-tied method may suffer from area and speed penalties. In addition,the benefits obtained by the body-tied method may diminish as SOIsilicon thicknesses scale downward because the increasing bodyresistance will make the body contact useless.

Another known body method for controlling V_(th) is channel regiondoping. Despite raising the V_(th), however, channel implants reduce thedepletion ability of an SOI device, thereby incurring performancedegradation from the FBE.

Another commonly used method for FBE reduction is to fully deplete (FD)the channel region of the SOI device by thinning the silicon thickness.The FD SOI device enables an additional impact ionization (I-I) inducedcarrier sweep out of the channel, thereby suppressing the FBE.Substantial suppression of the FBE in the transistor channel regionsignificantly enhances voltage threshold control.

Biasing the body region of an SOI transistor is conventionally animportant part of device V_(th) control, and thinning the silicon bodythickness has become a preferred method that contributes to V_(th)control. However, there is still a need for SOI technology with thecapacity to provide sufficient back gate bias to achieve desired V_(th)values.

Another known and accepted method of achieving a desired V_(th) is tomodify the gate electrode work function by modifying the materialcomposition of the gate electrode. FIGS. 1 a and 1 b show known devices100 and 102, in which the gate electrode 104 material composition, andcorrespondingly the gate electrode 104 work function, is varied tocontrol the voltage threshold of the devices. The CMOS structure 100shown in FIG. 1 a is disclosed by Polishchuk, et al. in a paper entitled“Dual Work Function Metal Gate CMOS Transistors by Ni-TiInterdiffusion,” IEEE Electron Device Letters, Vol. 23, No. 4, April2002, incorporated herein by reference. FIG. 1 a shows a gate electrode104 comprising nickel and titanium over the PMOS region 106 andcomprising titanium over the NMOS region 108.

The FD SOI transistors 102 shown in FIG. 1 b and disclosed by H.Wakabayashi in a paper entitled “A Novel W/TiNx Metal Gate CMOSTechnology Using Nitrogen-Concentration-Controlled TiNx Film,”IEEE IEDM,Dec 1999, which paper is incorporated by reference herein, have gateelectrode 104 material compositions of tungsten W, titanium Ti, a firstconcentration of nitrogen N and a second concentration of nitrogen Nx.The variation of material composition varies the gate work function ofeach gate electrode 104, thereby varying the voltage threshold of the FDSOI transistors 102.

FIGS. 1 a and 1 b show gate electrode material composition variationwithin a small region of the chip. It is difficult, however, to applydifferent gate work function materials for SOI core applications and I/Odevice applications on the same chip, for example. In the conventionalcircuit application, the threshold voltage for a 3.3 eV I/O device isabout 0.65 eV and the threshold voltage for a 1.0 eV core device isabout 0.2 eV. The target threshold voltages are achieved by using a wellor a pocket implantation in the bulk substrate. However, for afully-depleted SOI device, the threshold voltage cannot be adjusted bythe channel or pocket implantation because heavy substrate concentrationwill turn the FD device into a partially depleted device and degrade theperformance. One method to achieve a different threshold voltage for afully depleted SOI device is to change the gate work function. This canbe demonstrated with reference to the following formula:

${Vth} = {\underset{V_{FB}}{\Phi_{m\; s} - \frac{Q_{f}}{C_{ox}}} + \Phi_{s} + \frac{\sqrt{{2\; ɛ\; {qN}_{A{(D)}}\Phi_{s}}\;}}{Cox}}$

For example, if we keep the Na (substrate concentration) constant, wemay need another variable to control the threshold voltage to a desiredvalue in a different application. The gate workfunction (Φm) is a goodcandidate for V_(th) tuning because recently metal gate development hasbecome mainstream technology. This is because metal gates not onlyimprove gate resistance, but they also show better characteristics,compared to polysilicon, in integrating with high-k dielectricmaterials, as illustrated in FIG. 1 c.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, andtechnical advantages are generally achieved, by preferred embodiments ofthe present invention, which provide for a fully depleted SOI multiplethreshold voltage application. In other embodiments, the presentinvention provides for an integrated circuit having fully depleted SOImultiple threshold voltage devices and non-SOI multiple thresholdvoltage devices.

In accordance with an illustrative embodiment of the present invention,an integrated circuit comprises a substrate and a buried dielectricformed in said substrate. The buried dielectric has a first thickness ina first region, a second buried dielectric thickness in a second region,and a step between said first and second regions. A semiconductor layeroverlies said buried dielectric.

In accordance with another illustrative embodiment of the presentinvention, a semiconductor chip (also known as a die) has a first regionand a second region. The semiconductor chip also has a substrate and asemiconductor layer overlying the substrate. The semiconductor chipfurther comprises a buried dielectric under the semiconductor layerformed at least partially in said substrate. The buried dielectric has afirst thickness in said first region and a second thickness in saidsecond region separated by a step. A first transistor has a first gateelectrode and a second transistor has a second gate electrode formed insaid first region. A third transistor has a third gate electrode and afourth transistor has a fourth gate electrode formed in said secondregion.

In accordance with another illustrative embodiment of the presentinvention, a semiconductor chip comprises a substrate. The substratecomprises at least one buried dielectric, the buried dielectric having afirst buried dielectric thickness in a first V_(th) region greater thana second buried dielectric thickness in a second V_(th) region, whereinthe difference between the first V_(th) and the second V_(th) is about0.15˜0.45 eV. Specific examples would include a core region having aV_(th) of about 0.2 eV (less than 1.8 eV) and an I/O region having aV_(th) of about 0.65 eV, wherein the barrier dielectric thickness of thecore region is greater than the barrier dielectric thickness of the I/Oregion. For other applications, the threshold voltage of the I/O regionmay be greater than 1.8 eV.

In accordance with another illustrative embodiment of the presentinvention, a semiconductor chip comprises a substrate. The substratecomprises at least one buried dielectric, the buried dielectric having afirst buried dielectric thickness in a core region greater than a secondburied dielectric thickness in an I/O region. The chip also comprises afirst fully depleted silicon on insulator p-channel metal oxidesemiconductor (FD SOI PMOS) transistor in the core region, the first FDSOI PMOS transistor with a first gate electrode overlying a first gatedielectric, the first gate electrode having a first work function. Thesemiconductor chip further comprises a first FD SOI n-channel metaloxide semiconductor (NMOS) transistor in the core region, the first FDSOI NMOS transistor with a second gate electrode overlying a second gatedielectric, the second gate electrode having a second work function. Thesemiconductor chip further comprises a second FD SOI PMOS transistor inthe input/output (I/O) region, the second FD SOI PMOS transistor with athird gate electrode overlying a third gate dielectric, the third gateelectrode having a third work function. The semiconductor chip stillfurther comprises a second FD SOI NMOS transistor in the input/outputregion, the second FD SOI NMOS transistor with a fourth gate electrodeoverlying a fourth gate dielectric, the fourth gate electrode having afourth work function. The first, second, third and fourth work functionsare substantially different from one another.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIGS. 1 a and 1 b show known dual work function metal gate transistors;and FIG. 1 c graphically illustrates the relationship between thresholdvoltage and gate work function;

FIGS. 2 a-2 c show cross-sectional views demonstrating steps in a firstmethod of manufacturing in accordance with a first illustrativeembodiment of the present invention;

FIG. 2 d shows a cross-sectional view of a buried dielectric step;

FIG. 2 e shows a first illustrative embodiment of the present invention;

FIG. 2 f shows a second illustrative embodiment of the presentinvention; and

FIGS. 3 a-3 h show cross-sectional views demonstrating steps of a secondmethod of manufacturing in accordance with a third illustrativeembodiment of the present invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments arediscussed in detail below. It should be appreciated, however, that thepresent invention provides many applicable inventive concepts that canbe embodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative of specific ways to makeand use the invention, and do not limit the scope of the invention.

The present invention will be described with respect to preferredembodiments in a specific context, namely a fully depleted SOI multiplethreshold voltage application. The invention may also be applied,however, to other semiconductor devices and semiconductor applicationshaving a need for multiple threshold voltages on the same substrate.

A substrate 200, shown in FIG. 2 a, comprises a semiconductor substratematerial. The substrate material is preferably a p-type dopedsubstantially crystalline silicon material with a crystal orientation of<100>. Alternatively, the substrate 200 may be doped n-type and have acrystal orientation the same as the p-type doped substrate, or othercrystal orientations such as <111>and <110>, for example. The substrate200 may comprise any material suitable as a semiconductor substrate,such as gallium arsenide, indium phosphide, silicon, germanium, carbon,and combinations thereof, including buffer layers comprising gradedproportions of semiconductor materials such as a graded silicongermanium buffer layer, for example. The substrate 200 may also be astrained semiconductor such as strained silicon or ceramic wafer, forexample.

The substrate 200 has a core region 202 and an input/output (I/O) region204. Illustrative embodiments of the present invention includesubstrates with any number of regions having any number of voltagethreshold requirements. For example, illustrative embodiments includesubstrates with regions designated for low noise applications.Transistors formed in I/O regions of semiconductor chips typically havea higher threshold voltage than transistors in the core regions of thesame chip, for example.

Examples of I/O devices may include tri-state buffers, input buffers,and output buffers, for example. I/O devices may include electrostaticdischarge (ESD) circuitry and may provide a tolerance to multiplevoltages. I/O regions, such as the I/O region 204, are typically formedon the outskirts of a chip, in parts remote from the center. Coreregions, such as the core region 202, are typically located in regionsof a chip that are proximate the center. Other arrangements of the I/Oand core regions are contemplated, however. Core regions 202 typicallyinclude transistors having high speed and low power requirements forlarge scale integrated (LSI) circuits (e.g., ULSI, VLSI), such asprocessors, controllers, and application specific integrated circuits(ASICs), for example.

Referring to FIG. 2 b, a mask 206 is deposited over the I/O region 204of the substrate 200, exposing the core region 202 of the substrate 200.The substrate 200 is subjected to implantation of a dielectric material208 into exposed portions of the silicon substrate 200, forming a burieddielectric 210. The implantation process is preferably an oxygen implantprocess, such as separation by implanted oxygen (SIMOX). Theimplantation process may alternatively be separation by implantednitrogen (SIMNI), separation by implanted oxygen and nitrogen, orinternal thermal oxidation (ITOX), for example. The SIMOX implantationstep preferably includes ion implantation of oxygen (e.g., 1.8×10¹⁸ percm²) with substrate temperatures greater than about 600 degrees Celsius.

The implantation of other materials such as nitrogen and hydrogen may beperformed concurrently or subsequently. For example, the burieddielectric 210 may be a nitrided oxide or a hydrogenated oxide compositeof silicon oxide. Implanting nitrided oxide contributes to theprevention of impurity dopant diffusion into the buried oxide, therebypreventing device performance degradation. Impurity dopant diffusion mayoccur from impurity dopants implanted during a well formationmanufacturing step, such as for n-type wells (n wells), for example. Asanother example, carbon may be implanted to form a carbide layer.

Referring to FIG. 2 c, the mask 206 is stripped and dielectric material208, preferably oxygen, is again implanted into the core region 202 andthe I/O region 204 of the silicon substrate 200. The second oxygenimplantation step extends the buried dielectric 210 into the I/O region204 of the silicon substrate 200 and thickens the buried dielectric 210in the core region 202. The thickness t_(core) of the buried dielectric210 in the core region 202 is preferably about 1000 angstroms. Thethickness of the buried dielectric 210 in the I/O region 204 t_(I/O) ispreferably about 300 angstroms. The thickness of the buried dielectricmay alternatively range between about 50 angstroms and about 2000angstroms.

After implantation, the SIMOX process includes a high temperature (e.g.,about 1300 degrees Celsius) anneal of the substrate. In otherillustrative embodiments, the steps of masking and buried dielectricimplantation are repeated any number of times, forming a burieddielectric of any number of thicknesses in any number of regions on thewafer.

The buried dielectric 210 isolates a semiconductor layer 222 from thewafer substrate 200. The wafer 223, comprising silicon 222 over aninsulator 210, is conventionally referred to as a silicon-on-insulator(SOI) wafer. The semiconductor layer 222 commonly has a thickness 225 ofabout 200 angstroms. However, the thickness 225 may range between about50 angstroms and about 500 angstroms.

Although a buried dielectric step 215 in the dashed box 211 is shownwith right angles, the step 211 preferably has a sloped sidewall 212, asshown in FIG. 2 d. FIG. 2 d is an enlarged view of the dashed box 211.The slope of the sidewall 212 is a thickness gradient, which isdependent on circuit design. For example, the gradient region may be aforbidden region for active devices but dummy devices or passive devicesmay be formed therein. This is because the gradient region may containdislocations and a non-uniform capacitance, which may result in unstableelectric performance of active devices. In illustrative embodiments,steps in the buried oxide may have different thickness gradients,however, each thickness gradient (in the vertical direction) preferablyranges between about 50 angstroms and about 200 angstroms. In someinstances, a small spacing (less than about 0.3 um) may be desiredbetween two active regions, one with a thin barrier dielectric andanother with a thick barrier dielectric. In those instances, the stepmay be preferably no greater than about 1/10 of the spacing to avoid thethreshold voltage fluctuation due to a closed active region.

Subsequent manufacturing steps form the first illustrative embodimentshown in FIG. 2 e. Shallow trench isolation structures 220 isolate FDSOI transistors 214. The transistors 214 over the thicker portion of theburied dielectric 210 in the core region 202 will have a lower thresholdvoltage than the transistors 214 over the thinner portion of the burieddielectric 210 in the I/O region 204.

Varying the thickness of the buried dielectric 210 in different regions202 and 204 of the same substrate 200 provides substantial control ofthe voltage threshold of the FD SOI devices 214. For each transistor214, the underlying buried dielectric 210 acts as a capacitor dielectricbetween the anode, represented by the well or body region 213, and thecathode, represented by the substrate 200 underlying the burieddielectric 210, respectively. Varying the buried dielectric 210thickness varies the capacitance tied to the transistor channel regionin the well region 213, thereby providing a different voltage thresholdto the FD SOI devices 214 according to region 202 or 204.

An FD SOI device 214 in the I/O region 204 has a higher possible V_(th)than a substantially similar device 214 in the core region 202 becauseof the difference in buried dielectric 210 thickness. In general, athinner buried dielectric will provide a larger V_(th) tuning range, anda thicker buried dielectric will provide a smaller V_(th) tuning range.

In other illustrative embodiments, variation of the buried dielectricthickness is not limited to variation by region. The buried dielectricthickness may be varied on a chip or a wafer as desired for any numberof areas having any number of sizes. Although the buried dielectricthickness is preferably varied in accordance with voltage thresholdrequirements for FD SOI devices, the buried dielectric thickness mayalternatively be varied in accordance with other applicationrequirements relating to semiconductor device operation, such astemperature (e.g., SOI self heating effect), current, and noise, forexample.

Ion implantation steps that form the n-type or p-type well regions 213in the semiconductor material 222 overlying the buried dielectric 210may produce phosphorus or boron doped silicon oxide in top regions ofthe buried dielectric 210. The diffusion of III-V type impurities intothe buried dielectric 210 from overlying well regions 213 may alsocontribute to doped silicon oxide in regions of the buried dielectric210.

A second illustrative embodiment shown in FIG. 2 f shows more than twoburied dielectric 209 thicknesses for regions CORE, LP, and I/O on thesame wafer substrate 200. The FD SOI transistors subsequently formed inthe silicon substrate 222 over the buried dielectric 209 will havedifferent V_(th) in accordance with the underlying thickness of theburied dielectric 209. Preferably, FD SOI transistors formed overlyingthe thickest portion of the buried dielectric 209 will have a lowerV_(th) than FD SOI transistors formed in the LP region or the I/Oregion. FD SOI transistors formed in the LP region will have a higherV_(th) than the transistors formed in the CORE region. The FD SOItransistors formed in the I/O region will have a higher V_(th) than thetransistors in the LP region and the CORE region.

A second method in accordance with a third illustrative embodiment,shown in FIGS. 3 a-3 h, comprises the buried dielectric 210 of the firstillustrative embodiment. In FIG. 3 a, shallow trench isolationstructures 220 are formed in the silicon region 222 overlying the burieddielectric 210. Alternatively, other isolation structures (e.g., mesaisolation and LOCOS isolation) may be used. The silicon region 222 overthe buried dielectric 210 is about 200 angstroms thick.

A gate dielectric 224 comprising silicon oxide is deposited. Thethickness of the gate dielectric 224 is about 100 angstroms and mayalternatively range between about 20 angstroms and about 100 angstroms.The gate dielectric may alternatively be formed of a high k dielectricmaterial having a high dielectric constant, greater than about 4.0. Thehigh k dielectric material may be a metal dielectric, including metaloxide such as Al₂O₃, Ta₂O₅, ZrO₂, and HfO₂, or HfSi for example. Variouskinds of treatment can be used on high k dielectrics such as NH₃ anneal,O⁻ anneal, NO anneal, and N₂O anneal, all well known.

A mask material such as a photoresist (not shown), covers the gatedielectric 224 in the I/O region 204, and a portion of the exposed gatedielectric 224 in the core region 202 is removed, as shown in FIG. 3 b.The resulting thickness of the gate dielectric 224 in the core region202 is about 8 angstroms and may alternatively range between about 8angstroms and about 20 angstroms. For emphasis, the step 226 formedbetween the core region 202 and the I/O region 204 is shown on a largerscale.

The thicker portion of the gate dielectric 224 will enable a highervoltage threshold in the FD SOI devices that will subsequently be formedin the I/O region 204. In contrast, the FD SOI devices to be formed inthe core region 202 will have a thinner gate dielectric 224 and acorresponding lower voltage threshold.

A layer of polysilicon 228 is deposited on the gate dielectric 224 asshown in FIG. 3 c. Although, a polysilicon step (not shown) may formover the gate dielectric step 226 in the polysilicon surface 230, thepolysilicon step is a relatively insignificant surface feature and thepolysilicon surface 230 is represented in FIG. 3 c as beingsubstantially planar for illustrative purposes.

FIG. 3 d shows subsequent steps of forming a photoresist material 232 onthe polysilicon 228. Unmasked portions 234 of the polysilicon 228 aredoped 236 with an n-type dopant, forming n-doped polysilicon region 234.The dopant is preferably implanted by known ion implantation methodssuch as plasma immersion ion implantation (PIII) or metal plasmaimmersion ion implantation (MePIII), for example. The dopant ispreferably phosphorus and may alternatively be arsenic, boron, mescaline(BF₂), hydrogen, nitrogen, oxygen, argon, or combinations thereof.

As shown in FIG. 3 e, a first metal layer 238 and a second metal layer240 are consecutively deposited over the gate dielectric 224. Thethickness of the first metal layer 238 is about 50 angstroms and thethickness of the second metal layer 240 is about 200 angstroms. Themetal layers 238 and 240 are deposited using known deposition methodssuch as evaporation, sputtering, or various types of chemical vapordeposition such as plasma enhanced chemical vapor deposition, forexample. The first metal layer 238 preferably comprises titanium and thesecond metal layer 240 preferably comprises platinum. However, the first238 and second 240 metal layers may alternatively comprise nickel,palladium, platinum, iridium, ruthenium, rhodium, molybdenum, hafnium,aluminum, cobalt, tungsten, or combinations thereof, for example.Combinations may include metal alloys such as binary metal alloys, metalsilicides, metal silicon nitrides, doped metal alloys, and dopedsilicide alloys, for example.

Subsequent photolithography steps mask a portion of the second metallayer 240 in the I/O region 204, and the exposed portion of the secondmetal layer 240 in the core region 202 is removed, as shown in FIG. 3 f.A wet etch or reactive ion etching may be used to remove portions of thesecond metal layer 240.

A thermal anneal at about 500° C. for about 10 minutes causes the metals238 and 240 to diffuse into the undoped 228 and doped 234 regions of thepolysilicon, as shown in FIG. 3 g. The anneal process produces a silicontitanium alloy gate electrode 250 and an n-doped silicon titanium alloygate electrode 252 in the core region 202. The anneal process alsoproduces a titanium, platinum and silicon alloy 254 and an n-dopedtitanium, platinum and silicon alloy 256 in the I/O region 204. In theillustrated embodiments, only a single gate electrode doping step isillustrated. One skilled in the art will recognize, however, that thegate electrodes can have differing doping concentrations and differingdoping impurities. This can be accomplished, e.g., by multiple dopingsteps and by in-situ doping during deposition of gate polysilicon layer228. Preferably, the ratio of doping concentration between the gateelectrodes is in the order of 10⁵ or less.

FIG. 3 h shows the structure of FIG. 3 g after further processingproduces FD SOI PMOS transistors 260, 261 and FD SOI NMOS transistors262, 263. Varying the material composition, and thereby the workfunction of the gate electrodes 250, 252, 254, and 256, provides acorresponding difference in voltage threshold between the FD SOI devices260, 261, 262, and 263. The voltage thresholds of the FD SOI transistors260, 261, 262, and 263 in FIG. 3 h are partially controlled by the workfunction of the gate electrodes 250, 252, 254, and 256. The gateelectrode 250 has a work function ranging between about 4.7 eV and about5.0 eV. The gate electrode 254 has a work function ranging between about4.4 eV and about 4.7 eV. The gate electrode 252 has a work functionranging between about 4.2 eV and about 4.5 eV. The gate electrode 256has a work function ranging between about 4.5 eV and about 4.8 eV.

The combination of buried dielectric 210 thickness variation, gatedielectric 224 thickness variation, and the variation of gate electrode250, 252, 254, and 256 work functions, provides a high degree of controlof the voltage threshold variation of the FD SOI transistors 260, 261,262, and 263 and other devices on the same chip die 200 or in the samewafer.

The FD SOI transistors 260, 261, 262, 263 used in the illustrativeembodiments described herein are meant to be illustrative of depletedsubstrate devices in general. The present invention may also be appliedto partially depleted devices such as partially depletedsilicon-on-insulator (PD SOI) transistors, for example. Other devices inillustrative embodiments of the present invention include field effecttransistors (FET) such as metal oxide semiconductor FETs (MOSFETs),metal semiconductor FETs (MESFETs), thin film transistors (TFTs),strained channel transistors, and double gate MOSFETs, for example.Although the present invention is suitable for any technology node, thepresent invention is preferably suitable for the 65 nm node and smallertechnology nodes.

Contacts 280, such as those coupled at the source 270, drain 272 andgate 274 regions of the transistor 263, for example, alter or otherwiseform new work functions in the transistors. For example, silicide formedin the source region 270 of the FD SOI NMOS 263, provides a fifth workfunction in the source region as a result of the diffusion of thetungsten material in the contact 280 with the doped polysilicon in thetop portion of source region 270. Another gate work function is providedby diffusion of the tungsten material in the contact 282 with then-doped polysilicon and titanium of the gate electrode 256 in the topportion of the gate electrode 274.

The preferred embodiments of the present invention provide a significantadvantage relating to the control of the voltage threshold ofsemiconductor devices, and specifically to fully depletedsilicon-on-insulator devices in different circuit applications on achip. The present invention may be used to include devices requiringthin and ultra-thin buried oxides on a single die, for example.Applications include core applications, low power applications, and I/Oapplications, for example. Improved control of the voltage threshold ofdevices in different applications provides more control of the draininduced barrier lowering in FD SOI devices, and enhanced device andcircuit performance.

An advantage of the preferred embodiments of the present invention isthat the buried dielectric thickness may be varied according toapplications having transistors with different desired voltagethresholds, e.g., core applications, low power applications, and I/Oapplications. Another advantage is that different buried oxidethicknesses in the same wafer may be used to provide V_(th) adjustmentsubstantially reserved for FD SOI back-gate biased devices requiringV_(th) adjustment, e.g., core applications, low power applications, andI/O applications.

Although preferred embodiments of the present invention and theiradvantages have been described in detail, it should be understood thatvarious changes, substitutions and alterations can be made hereinwithout departing from the spirit and scope of the invention as definedby the appended claims. For example, it will be readily understood bythose skilled in the art that a fully depleted SOI multiple thresholdvoltage application may be varied while remaining within the scope ofthe present invention.

Moreover, the scope of the present application is not intended to belimited to the particular embodiments of the process, machine,manufacture, composition of matter, means, methods and steps describedin the specification. As one of ordinary skill in the art will readilyappreciate from the disclosure, processes, machines, manufacture,compositions of matter, means, methods, or steps, presently existing orlater to be developed, that perform substantially the same function orachieve substantially the same result as the corresponding embodimentsdescribed herein may be utilized according to the present invention.Accordingly, the appended claims are intended to include within theirscope such processes, machines, manufacture, compositions of matter,means, methods, or steps.

1. An integrated circuit comprising: a substrate; a buried dielectricformed in said substrate, the buried dielectric having a first thicknessin a first region and a second thickness in a second region, the burieddielectric having a substantially planar top surface; and asemiconductor layer overlying said buried dielectric.
 2. The integratedcircuit of claim 1, wherein a substantial portion of the substratecomprises crystalline silicon.
 3. The integrated circuit of claim 1,wherein said semiconductor layer overlying the buried dielectriccomprises strained silicon.
 4. The integrated circuit of claim 1,wherein said semiconductor layer overlying the buried dielectriccomprises a germanium containing semiconductor material.
 5. Theintegrated circuit of claim 1, further comprising a step between saidfirst and second regions, wherein said step is about 200 angstroms orless.
 6. The integrated circuit of claim 1, further comprising a fullydepleted silicon-on-insulator transistor formed in said semiconductorlayer.
 7. The integrated circuit of claim 1, wherein the burieddielectric comprises silicon oxide.
 8. The integrated circuit of claim1, wherein the buried dielectric comprises nitrided oxide.
 9. Theintegrated circuit of claim 1, wherein the buried dielectric compriseshydrogenated oxide.
 10. The integrated circuit of claim 1, wherein theburied dielectric comprises Al_(x)O_(y), wherein x is about 2 and y isabout
 3. 11. The integrated circuit of claim 1, wherein the burieddielectric comprises silicon carbide.
 12. The integrated circuit ofclaim 1, wherein the first region is designated for a first applicationrequiring a first threshold voltage and wherein the second region isdesignated for a second application requiring a second thresholdvoltage.
 13. The integrated circuit of claim 12, wherein the firstapplication is a core application having the first threshold voltage andthe second application is an input/output application having the secondthreshold voltage, wherein the difference between the first thresholdvoltage and the second threshold voltage is about 0.45 eV or less. 14.The integrated circuit of claim 13, wherein the first threshold voltageis less than about 1.8 eV.
 15. The integrated circuit of claim 5,wherein said step is a gradient region and further comprising aforbidden region overlying said gradient region wherein no activedevices are formed.
 16. A semiconductor chip having a first region and asecond region, the semiconductor chip comprising: a substrate; asemiconductor layer overlying the substrate; a buried dielectric underthe semiconductor layer, the buried dielectric having a first thicknessin said first region and a second thickness in said second region, theburied dielectric having a substantially planar top surface; a firsttransistor having a first gate electrode and a second transistor havinga second gate electrode formed in said first region; and a thirdtransistor having a third gate electrode and a fourth transistor havinga fourth gate electrode formed in said second region.
 17. Thesemiconductor chip of claim 16, wherein: said first gate electrode isformed of a first material and has a first concentration of a firstimpurity therein and said second gate electrode is formed of a secondmaterial and has a second concentration of a second impurity therein;and said third gate electrode is formed of a third material and has athird concentration of a third impurity therein and said fourth gateelectrode is formed of a fourth material and has a fourth concentrationof a fourth impurity therein.
 18. The semiconductor chip of claim 17,wherein said first material and said third material are substantiallythe same.
 19. The semiconductor chip of claim 17, wherein said secondmaterial and said fourth material are substantially the same.
 20. Thesemiconductor chip of claim 17, wherein said first and secondconcentrations have a ratio equal to about 105 or less.
 21. Thesemiconductor chip of claim 17, wherein said third and fourthconcentrations have a ratio equal to about 105 or less.
 22. Thesemiconductor chip of claim 17, wherein said first and third impuritiesare the same impurity.
 23. The semiconductor chip of claim 17, whereinsaid second and fourth impurities are the same impurity.
 24. Thesemiconductor chip of claim 17, wherein said first and third gateelectrodes comprise a silicide of silicon and a first metal and whereinsaid second and fourth gate electrodes comprise a silicide of siliconand a second metal.
 25. The semiconductor chip of claim 24, wherein saidsecond and fourth gate electrodes further comprise said first metal. 26.The semiconductor chip of claim 16, further comprising: a gatedielectric having a first gate dielectric thickness underlying saidfirst and second gate electrodes; and a gate dielectric having a secondgate dielectric thickness underlying said third and fourth gateelectrodes, wherein said second thickness varies from said firstthickness by a predetermined amount.
 27. The semiconductor chip of claim16, wherein the first transistor has a first gate dielectric thicknessthat is thinner than the second transistor's gate dielectric thickness.28. The semiconductor chip of claim 16, wherein the first and third gateelectrodes comprise titanium.
 29. The semiconductor chip of claim 17,wherein the third and fourth gate electrodes comprise platinum.
 30. Thesemiconductor chip of claim 27, wherein the first gate dielectricthickness ranges between about 8 angstroms and about 20 angstroms. 31.The semiconductor chip of claim 27, wherein the second transistor's gatedielectric thickness ranges between about 20 angstroms and about 100angstroms.
 32. The semiconductor chip of claim 16, further comprising astep in said buried dielectric and wherein said step is a gradientregion and further comprising a forbidden region overlying said gradientregion wherein no active devices are formed.
 33. The semiconductor chipof claim 16, wherein the first transistor is a fully depletedsilicon-on-insulator p-channel metal oxide semiconductor transistor (FDSOI PMOS) with a first work function ranging between about 4.7electron-volts and about 5.0 electron-volts, the second transistor is anFD SOI n-channel metal oxide semiconductor (NMOS) device with a secondwork function ranging between about 4.2 electron-volts and about 4.5electron-volts, the third transistor is an FD SOI PMOS device with athird work function ranging between about 4.4 electron-volts and about4.7 electron-volts, and the fourth transistor is an FD SOI NMOS devicewith a fourth work function ranging between about 4.5 electron-volts andabout 4.8 electron-volts